import schemdraw
import schemdraw.elements as elm
from schemdraw import logic
from schemdraw import elements

# schemdraw.elements.sources.Source

# Not from Nand

schemdraw.theme('monokai')
with schemdraw.Drawing(show=False, file='NOT_FROM_NAND.svg') as d:
    d += (OUT := logic.Nand().label('NOT', 'right'))
    d += (JOIN := logic.Wire('-|').at(OUT.in1).to(OUT.in2).dot().label('IN'))
    d += (B := logic.Line().left(2).at(OUT.in2))

# AND from NAND and NOT
with schemdraw.Drawing(show=False, file='AND_FROM_NAND_AND_NOT.svg') as d:
    d += (OUT := logic.Nand().label('AND', 'right'))
    d.move_from(OUT.out, dx=-5)
    d += (NAND := logic.Nand())
    d += (JOIN := logic.Wire('-').at(OUT.in1).to(NAND.out))
    d += (JOIN := logic.Wire('-').at(OUT.in2).to(NAND.out))
    d += (A := logic.Line().left(2).at(NAND.in1).label('A'))
    d += (B := logic.Line().left(2).at(NAND.in2).label('B'))

# OR from NAND
with schemdraw.Drawing(show=False, file='OR_FROM_NAND.svg') as d:
    d += (NAND := logic.Nand().right().label('OR', 'right'))
    d.move_from(NAND.in1, dy=1, dx=-2)
    d += (NANDA := logic.Nand())
    d.move_from(NAND.in2, dy=-1, dx=-2)
    d += (NANDB := logic.Nand())
    d += (JOIN1 := logic.Wire('-').at(NANDA.out).to(NAND.in1))
    d += (JOIN2 := logic.Wire('-').at(NANDB.out).to(NAND.in2))
    d += (JOIN3 := logic.Wire('-').at(NANDA.in2).to(NANDA.in1).dot())
    d += (JOIN3 := logic.Wire('-').at(NANDB.in1).to(NANDB.in2).dot())
    d += (A := logic.Line().left(2).at(NANDA.in1).label('A'))
    d += (B := logic.Line().left(2).at(NANDB.in2).label('B'))

# XOR from NAND
with schemdraw.Drawing(show=False, file='XOR_FROM_NAND.svg') as d:
    d += (NAND := logic.Nand().right().label('XOR', 'right'))
    d.move_from(NAND.in1, dy=1, dx=-2)
    d += (NANDA := logic.Nand())
    d.move_from(NAND.in2, dy=-1, dx=-2)
    d += (NANDB := logic.Nand())
    d += (JOIN1 := logic.Wire('-').at(NANDA.out).to(NAND.in1))
    d += (JOIN2 := logic.Wire('-').at(NANDB.out).to(NAND.in2))
    d.move_from(NAND.out, dx=-8)
    d += (NANDC := logic.Nand())
    d += (JOIN3 := logic.Wire('-').at(NANDC.out).to(NANDA.in2))
    d += (JOIN4 := logic.Wire('-').at(NANDC.out).to(NANDB.in1))
    d += (JOIN5 := logic.Wire(shape='-|').at(NANDA.in1).to(NANDC.in1).dot())
    d += (JOIN6 := logic.Wire(shape='-|').at(NANDB.in2).to(NANDC.in2).dot())
    d += (A := logic.Line().left(2).at(NANDC.in1).label('A'))
    d += (B := logic.Line().left(2).at(NANDC.in2).label('B'))

# MUX from NAND and NOT
with schemdraw.Drawing(show=False, file='MUX_FROM_NAND_NOT.svg') as d:
    d += (NAND := logic.Nand().right().label('MUX', 'right'))
    d.move_from(NAND.in1, dy=1, dx=-2)
    d += (NANDA := logic.Nand())
    d.move_from(NAND.in2, dy=-1, dx=-2)
    d += (NANDB := logic.Nand())
    d += (JOIN1 := logic.Wire('-').at(NANDA.out).to(NAND.in1))
    d += (JOIN2 := logic.Wire('-').at(NANDB.out).to(NAND.in2))
    d.move_from(NAND.out, dx=-6)
    d += (NANDC := logic.Nand())
    d += (JOIN3 := logic.Wire('-').at(NANDC.out).to(NANDB.in1))
    d += (JOIN4 := logic.Wire('-|').at(NANDC.in2).to(NANDC.in1).dot())
    d.move_from(NANDC.out, dx=-3)
    d += (JOIN4 := logic.Wire('|-').at(NANDC.in1).to(NANDA.in2))
    d += (A := logic.Line().left(4).at(NANDA.in1).label('A'))
    d += (B := logic.Line().left(4).at(NANDB.in2).label('B'))
    d += (B := logic.Line().left(2).at(NANDC.in1).label('SEL'))

# DMUX from NAND and NOT
with schemdraw.Drawing(show=True, file='DEMUX_NAND.svg') as d:
    d += (OUTB := logic.Nand().right().label('DEMUX B', 'right'))
    d.move_from(OUTB.in1, dy=1)
    d += (OUTA := logic.Nand().right().label('DEMUX A', 'right'))
    d.move_from(OUTA.in1, dx=-2)
    d += (NANDA := logic.Nand())
    d.move_from(NANDA.in1, dy=-2)
    d += (NANDB := logic.Nand())
    d += (JOINOA := logic.Wire('-').at(OUTA.in2).to(OUTA.in1).dot())
    d += (JOINOB := logic.Wire('-').at(OUTB.in1).to(OUTB.in2).dot())
    d += (JOINA1 := logic.Wire('-').at(NANDA.out).to(OUTA.in1))
    d += (JOINB2 := logic.Wire('-').at(NANDB.out).to(OUTB.in2))
    d.move_from(NANDA.in2, dy=-0.5, dx=-2)
    d += (SELECTNAND := logic.Nand())
    d += (JOINSELECT := logic.Wire('-').at(SELECTNAND.in1).to(SELECTNAND.in2).dot())
    d += (JOINSELECTNANDA := logic.Wire('-').at(SELECTNAND.out).to(NANDA.in2))
    d.move_from(SELECTNAND.in2, dx=-2)
    d += (SS := logic.Wire('-').at(SELECTNAND.in1).to(SELECTNAND.in2).dot())
    d.move_from(SELECTNAND.in2, dy=-1, dx=-2)
    d += (SSB := logic.Wire('|-').at(SELECTNAND.in2).to(NANDB.in1))
    d.move_from(SELECTNAND.in1, dy=-1, dx=-4)
    d += (L1 := logic.Line().left(4).at(NANDB.in2))
    d += (L2 := logic.Line().left(4).at(NANDA.in1))
    d += (SSA := logic.Wire('|-').at(L1.end).to(L2.end).dot())
    d += (INPUT := logic.Line().left(3).at(L2.end).label('INPUT'))